The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Conventional memory single port devices typically are configured so that during any given clock cycle only a single memory operation, such as a read operation or a write operation, can be performed at a particular block of memory. Moreover, because write operations may require several clock cycles to complete, performance of various read operations may also be delayed for several clock cycles in conventional memories. In the context of some networking or switching applications, various data that is used for packet processing, for example control tables, forwarding tables and the like, are shared among various switching devices or switching cores of a single device. At times, these multiple devices and cores need to perform read and write operations in a particular memory block during the same clock cycle.
In some systems, various devices are provided with their own respective memories, however such a solution is expensive both in terms of the direct cost of additional memory as well as in terms of resources required to keep the different memories synchronized.
U.S. Pat. No. 8,514,651, entitled “Sharing Access to a Memory Among Clients”, and which is assigned to the present assignee and incorporated by reference herein in its entirety, describes a system and method in which two or more read requests to read data from a target memory bank shared by two or more clients are serviced during a single clock cycle. A first one of the read requests is serviced by permitting direct accesses to the target memory bank during a clock cycle. The additional read requests are also serviced in the clock cycle by using redundancy data to reconstruct data in the target memory bank without directly accessing the target memory bank.